1. Field of the Invention
This invention relates to the field of data processing. More particularly, this invention relates to cache memory circuits of the type that are typically used to provide short term, high speed storage for instruction words or data words.
2. Description of the Prior Art
FIG. 1 of the accompanying drawings illustrates a data processing system utilizing a cache memory circuit. An integrated circuit 2 is formed bearing a central processing unit core 4, a cache memory circuit 6 and a write buffer 8 among other components. The integrated circuit 2 is coupled to a random access memory 10 that provides the bulk of the storage capacity for the system.
In operation, when required by the central processing unit core 4, words representing instructions or data to be manipulated are read from the random access memory 10 and stored in the cache memory circuit 6. Subsequently, when the central processing unit core 4 needs to access one of these words, it first checks to see if it is present in the cache memory circuit 6. If the word is so present, then it may be accessed at high speed from this on-chip cache memory circuit 6 without having to make recourse to a slower off-chip access to the random access memory 10. There are various strategies for selecting which words should be held within the cache memory circuit 6 and how consistency should be maintained between the words stored within the cache memory circuit 6 (that may be subject to manipulation) and the corresponding words stored within the random access memory 10. With one strategy for maintaining consistency, the cache memory circuit is configured as a so called "write back cache".
In operation of such an arrangement, when the central processing unit core 4 wishes to access a particular word, a check is made within the cache memory circuit 6 to determine whether this word is stored there. If the word is stored in the cache memory circuit 6, then a cache hit has occurred. Following a cache hit, a high speed read or write operation to that word may be made. It is significant that if a write operation is made to the word, then this write operation is not at this stage made to the corresponding word stored within the random access memory 10. Accordingly, the instance of that word stored within the random access memory 10 becomes out of date and invalid.
The updating of out of date words within the random access memory 10 occurs when the corresponding words within the cache memory circuit 6 are being replaced to make way for other words to which it is more desirable to have high speed access. When words stored within the cache memory circuit 6 are so replaced, then they are written back to the random access memory 10 so updating the instances of the words stored within the random access memory 10. FIG. 2 of the accompanying drawings illustrates this process in more detail.
At step 12, when a cache miss occurs, then the write back process is entered. The first stage is to identify the cache row to be replaced at step 14. Various strategies may be employed to determine which cache row (a cache is typically organised in rows, each cache row storing a plurality of words) is to be replaced. A common strategy is to replace the cache row that was least recently accessed (used).
A so called "dirty flag" for the cache row indicates whether any of the words stored therein have been changed since they were read from the random access memory 10. If the dirty flag is set, then at steps 16 to 22 the four words currently stored within the selected cache row are written to the write buffer 8 during successive clock cycles (fclk) of the integrated circuit 2. The example of FIG. 2 assumes that such a change has occurred.
Once the old words have been safely written to the write buffer 8 for subsequent storage back to the random access memory 10, the clock signal of the integrated circuit 2 is synchronised to the external, slower memory clock signal (mclk) that drives the random access memory 10 at step 24. This switch of clock signals could be made earlier, but this would slow down the overall operation as it is best to keep using the faster clock signal (fclk) for as long as possible.
In steps 26, 28, 30 and 32 the new words from the random access memory 10 are read into the cache row on successive external clock cycles.
It will be seen from FIG. 2 that the writing back of the old words and the reading in of the new words takes in excess of (4.times.fclk)+(4.times.mclk). The writing back and reading in of the words of a cache row is controlled by cache control logic 34 within the cache memory circuit 6. This example assumes a different and faster fclk signal from the mclk signal. These signals could be the same.
FIG. 3 of the accompanying drawings illustrates the process shown in FIG. 2. The top four schematics illustrate the saving of successive words from the selected cache row to the write buffer. The bottom four illustrations illustrate the subsequent reading of four successive words from the random access memory 10.
The performance of a cache has a large impact upon the overall performance of a data processing system within which the cache is incorporated. Measures which improve the performance of a cache (e.g. its speed of operation) are highly advantageous.